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[bugfix] Allow late mcsat conflicts (wrt assigns)

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This commit is contained in:
Guillaume Bury 2017-04-07 15:13:27 +02:00
parent 5725cf5173
commit 7e95911dd8
1 changed files with 5 additions and 3 deletions
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8
src/core/internal.ml
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@ -657,9 +657,11 @@ module Make
(* look for the next node to expand *)
while
let q = get_atom !tr_ind in
(not (q.var.seen = Both)) ||
(q.var.v_level < conflict_level)
match Vec.get env.elt_queue !tr_ind with
| Atom q ->
(not (q.var.seen = Both)) ||
(q.var.v_level < conflict_level)
| Lit _ -> true
do
decr tr_ind;
done;